(1) Field of the Invention
The present invention relates to semiconductor processing for integrated circuits, and more particularly relates to a method for more accurately measuring overlay alignment errors to determine the process window. More specifically, the method allows one to implement interfield and intrafield overlay correction parameters during photoresist exposure in a step-and-repeat or step-and-scan exposure tool to more accurately align electrical interconnections over contact holes.
(2) Description of the Prior Art
Integrated circuits are formed in field areas on semiconductor substrates (wafers), such as single-crystal silicon (Si) substrates. After forming the discrete devices in and on the substrate, multilevels of electrically conducting layers and insulating layers are deposited and patterned to form the local and global interconnections for the integrated circuit. The patterned conducting layers, such as polycide and metal layers, are used to form the various levels of electrical interconnections. The interposing insulating layers, such as silicon oxide having contact holes or vias, are used to electrically insulate the various metal levels, while the contact holes or vias in the insulating layer provide connections between the various levels of conducting layers. As feature sizes decrease and circuit density increases, the accurate alignment of the various patterned layers becomes more critical for making reliable integrated circuits (ICs).
A patterned photoresist layer is usually used as an etching mask to pattern the conducting layers and to etch the contact holes in the insulating layers. In early technologies, after spin coating a photoresist layer on the wafer, the photoresist was exposed with radiation through a single mask to define an array of field (chip) areas on the wafer. Alignment marks formed on the wafer from a previous masking and etching step was used to align the next mask level for exposing the photoresist for patterning the underlying layer. However, as the wafer diameter increased from less than 25 millimeters (mm) in the late 1960s to the current 300 mm, and minimum feature sizes of the devices decreased to less than a micrometer, it became increasingly difficult to accurately align a patterned photoresist layer over an underlying patterned layer on the wafer within the required process window, using a single mask.
An alternative method currently in use is to expose the photoresist through a reticle using a step-and-repeat system (or step-and-scan system) that exposes the photoresist in fixed increments across the two-dimensional wafer surface to define an array of field (circuit) areas. The reticle, which contains the circuit pattern, is aligned to alignment marks in the kerf area adjacent to each field area on the wafer. One type of alignment pattern generally used is a rectangle or square, commonly referred to as box-in-box alignment. However as the circuit feature sizes decrease below a micrometer (um), it becomes increasingly difficult to ensure that the registration of one alignment mark on a reticle, when aligned to the alignment mark etched in the wafer from a previous reticle, results in an acceptable alignment of the circuit elements in the field (circuit) areas.
Several methods of improving registration between different levels during photoresist exposure using a step-and-repeat tool have been reported in the literature. For example, Pelegrini in U.S. Pat. No. 5,444,538 describes a method for measuring the registration error between two different step-and-repeat tools having a one-to-one and a two-to-one field area. Pelegrini's method allows one to mix and match steppers from different manufacturers. Another method of reducing the registration error during photoresist exposure with a step-and-repeat tool is described by Ueno, U.S. Pat. No. 5,731,113. Ueno's method calculates registration errors between first and second misalignment inspection marks and corrects the misalignment by taking one-half the sum of the maximum and minimum values to obtain a correction value.
In the current high-density technology, planar surfaces are desirable because of the shallow depth of focus (DOF) required to expose high-resolution photoresist images. Also, a planar surface is essential to anisotropically (directionally) plasma etch metal patterns without leaving residue that would otherwise remain in recesses in a non-planar underlying insulating layer and result in intralevel shorts. Unfortunately, when a blanket conducting layer (opaque layer) is deposited on the planar surface of a wafer, it is difficult to correlate the registration of the alignment marks with the actual alignment of the circuit elements in the field area when After Development Inspection (ADI) of the photoresist layer is performed, since the overlay is not visible in an optical microscope or a scanning electron microscope (SEM). Therefore, it is necessary to etch the conducting layer (opaque layer) and to perform an After Etch Inspection (AEI) to ensure the pattern is aligned within the process window. If the misalignment is too great, it is necessary to rework the product wafer by stripping th e conductive layer. This stripping may be difficult to achieve and is not cost effective. This misalignment is a problem on current product, such as DRAMs, SRAMs, and the like, where the overlay tolerance is only about 100 nanometers. (1.0.times.10.sup.-9 meters).
Since there may not be an accurate relation between the overlay of the alignment marks (box in box) in the kerf areas and the overlay of the circuit patterns in the field areas when design rules are tight, there is still a need in the semiconductor industry to provide a method for determining overlay error corrections for the alignment mark prior to exposing the photoresist on product wafers in a step-and-repeat tool.